Hardware, FPGA & RTL Design Engineer
Driving innovation in chip design and hardware engineering. Currently pursuing a concurrent B.Sc. and M.Sc. (Research Track) with a focus on FPGA-based reliability monitoring systems.
Research Track · Ariel University
Research focused on FPGA-based reliability monitoring systems and RTL / digital hardware design. Investigating fault detection methods for safety-critical silicon.
Specialization in Computer Engineering & VLSI · Ariel University
Comprehensive foundation across digital design, computer architecture, and CMOS/VLSI. Graduated with distinction and direct admission to the research track.
Case studies from coursework, lab capstones and research — each documented end-to-end with reports, simulations and measurements.
Digital Logic & Embedded Systems Design
A comprehensive technical design and implementation of a secure electronic locking system, from FSM specification through RTL and user interface integration.
VLSI & Analog Electronics
Final report detailing the design, simulation and analysis of complex analog circuits using industry-standard EDA tools.
Data-Driven Engineering & Debugging
Rigorous testing protocols for hardware systems — detailed measurement tables, empirical data collection and error analysis driving design decisions.
Embedded Systems Architecture & Simulation
System-level design of a smart embedded controller featuring real-time safety monitoring (overheat and no-motion detection), user profile management, and complex state machine logic.
Engineering Rigor
Every project above ships with extensive written documentation, EDA-level simulation and physical measurement. The work reflects an engineering culture of traceability — from specification to silicon to signed-off results.
Documentation
Hundreds of pages of design reports, schematics and verification plans.
Simulation
RTL, SPICE and behavioural simulation across corner cases before fabrication.
Real-world Testing
Bench measurements, FPGA validation and structured error analysis.
Short-form observations from the lab, research bench and design desk — notes on methodology, debugging insights and emerging ideas.
Balancing real-time reliability monitoring in FPGAs against the area, power and timing overhead it introduces.
Read NoteDocumenting the iterative process of meeting setup and hold constraints across corner cases for an FPGA-based reliability monitor.
Read NoteA concise reference of state-machine encoding styles, reset strategies and registered outputs that translate cleanly to silicon.
Read NoteYears of service in elite military roles forged engineering-critical soft skills — ownership, structured thinking, and the ability to deliver under pressure.
Duvdevan Unit
Ordnance Corps
Led and developed soldiers and junior commanders in demanding operational environments.
Planned, coordinated, and executed multi-team training programs end-to-end.
Made decisive calls in high-stakes scenarios where precision and reliability are non-negotiable.